RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC)
R01UH0575EJ0120 Rev. 1.20 Page 538 of 920
Dec 22, 2016
16.5.6 DTC Response Time
Table 16 - 12 lists the DTC Response Time. The DTC response time is the time from when the DTC activation
source is detected until DTC transfer starts. It does not include the number of DTC execution clocks.
Note that the response from the DTC may be further delayed under the following cases. The number of delayed
clock cycles differs depending on the conditions.
• When executing an instruction from the internal RAM
Maximum response time: 20 clocks
• When executing a DTC pending instruction (refer to 16.5.3 DTC Pending Instruction)
• Maximum response time: Maximum response time for each condition + execution clock cycles for the
instruction to be held pending under the condition.
• When accessing the TRJ0 register that a wait occurs
Maximum response time: Maximum response time for each condition + 1 clock
Remark 1 clock: 1/f
CLK (fCLK: CPU/peripheral hardware clock)
16.5.7 DTC Activation Sources
• After inputting a DTC activation source, do not input the same activation source again until DTC transfer is
completed.
• While a DTC activation source is generated, do not manipulate the DTC activation enable bit corresponding to
the source.
• If DTC activation sources conflict, their priority levels are determined in order to select the source for activation
when the CPU acknowledges the DTC transfer. For details on the priority levels of activation sources, refer to
16.3.3 Vector Table.
Table 16 - 12 DTC Response Time
Minimum Time Maximum Time
Response Time 3 clocks 19 clocks
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