RL78/G1H CHAPTER 24 SAFETY FUNCTIONS
R01UH0575EJ0120 Rev. 1.20 Page 783 of 920
Dec 22, 2016
24.3.3 RAM parity error detection function
The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit
data in the RL78/G1H’s RAM. By using this RAM parity error detection function, the parity bit is appended when
data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset
when a parity error occurs.
24.3.3.1 RAM parity error control register (RPECTL)
This register is used to control parity error generation check bit and reset generation due to parity errors.
The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 24 - 7 Format of RAM parity error control register (RPECTL)
Caution The parity bit is appended when data is written, and the parity is checked when the data is read.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas
where data access is to proceed before reading data.
The RL78’s CPU executes look-ahead due to the pipeline operation, the CPU might read an
uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM area
+ 10 bytes when instructions are fetched from RAM areas.
Remark 1.
The parity error reset is enabled by default (RPERDIS = 0).
Remark 2. Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error occurs.
If the parity error reset is enabled (RPERDIS = 0) while RPEF = 1, a parity error reset occurs when RPERDIS
is cleared (0).
Remark 3. The RPEF flag in the RPECTL register is set (1) by RAM parity errors and cleared (0) by writing 0 to it or by
any reset source. When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is
read.
Remark 4. General-purpose registers are not included in the range of RAM parity error detection.
Address: F00F5H After reset: 00H R/W
Symbol<7>654321<0>
RPECTLRPERDIS000000RPEF
RPERDIS Parity error reset mask flag
0 Enable parity error resets.
1 Disable parity error resets.
RPEF Parity error status flag
0 No parity error has occurred.
1 A parity error has occurred.
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