RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 461 of 920
Dec 22, 2016
Note 1. When the WTIMn bit (bit 3 of IICA control register n0 (IICCTLn0)) = 1, an interrupt request occurs at the falling edge of
the ninth clock. When WTIMn = 0 and the extension code’s slave address is received, an interrupt request occurs at the
falling edge of the eighth clock.
Note 2. When there is a chance that arbitration will occur, set SPIEn = 1 for master device operation.
Remark 1. SPIEn: Bit 4 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
Table 15 - 4 Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration Interrupt Request Generation Timing
During address transmission At falling edge of eighth or ninth clock following byte
transfer
Note 1
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer When stop condition is generated (when SPIEn = 1)
Note 2
When data is at low level while attempting to generate a restart condition At falling edge of eighth or ninth clock following byte
transfer
Note 1
When stop condition is detected while attempting to generate a restart
condition
When stop condition is generated (when SPIEn = 1)
Note 2
When data is at low level while attempting to generate a stop condition At falling edge of eighth or ninth clock following byte
transfer
Note 1
When SCLAn is at low level while attempting to generate a restart
condition
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