RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 290 of 765
Mar 7, 2023
6.9.4 Operation as two-channel input with one-shot pulse output function
By using signal input to two pins (TI0n and TI0p), a one-shot pulse having any delay pulse width can be generated.
The delay (output delay time) and one-shot pulse width can be calculated by the following expressions.
Delay time = {Set value of TDR0n (master) + 2} × count clock period
One −shot pulse active −level width =
count clock period × ((10000H + TSR0p: OVF) + (capture value of TDR0p (slave) + 1)
Caution The TI0n and TI0p pin inputs are each sampled using the operation clock (f
MCK
) selected with the
CKS0n1 bit of the timer mode register 0n (TMR0n), so an error of one cycle of the operation clock
(f
MCK
) per pin occurs.
The master channel should be operated in the one-count mode to start counting the delays (output delay time) upon
detection of a valid edge of the master channel TI0n pin input used as the start trigger. Upon detection of a start trigger
(valid edge of TI0n pin input), the master channel loads the value of timer data register 0n (TDR0n) to the timer count
register 0n (TCR0n), and performs counting down in synchronization with the count clock (f
TCLK
). When TCR0n = 0000H,
the master channel outputs INTTM0n and outputs the active level from the TO0p pin. It stops counting until the next start
trigger is detected.
The slave channel should be operated in the capture mode to set the one-shot pulse to the inactive level upon detection
of a valid edge of the slave channel TI0p pin input used as the end trigger.
Upon detection of an end trigger (valid edge of TI0p pin input), the slave channel transfers (captures) the count value of
the TCR0p register to the TDR0p register, and clears it to 0000H. Simultaneously, the slave channel outputs INTTM0p
and the inactive level from the TO0p pin. Here, if the counter overflow has occurred, the OVF bit in the timer status
register 0p (TSR0p) is set; if not, the OVF bit is cleared. After this, the same steps are repeated.
When the count value is captured to the TDR0p register, the OVF bit in the TSR0p register is updated depending on the
overflow status during the active level period, which allows the overflow status of the captured value to be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSR0p register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Instead of using the TI0n pin input, the software operation (TS0n = 1) can be used as a start trigger for the master
channel startup detection.
Remark n: Master channel number (n = 0, 2), p: Slave channel number (p = 3)
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