Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 15 STANDBY FUNCTION
R01UH0959EJ0110 Rev.1.10 Page 629 of 765
Mar 7, 2023
15.3.2 STOP mode
(1) STOP mode setting and operating status
The STOP mode is set by executing the STOP instruction.
Caution Because the interrupt request signal is used to clear the STOP mode, if the interrupt mask flag is 0
(the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal is
generated), the STOP mode is immediately cleared if set when the STOP instruction is executed in
such a situation. Accordingly, once the STOP instruction is executed, the system returns to its
normal operating mode after the elapse of release time from the STOP mode.
The operating status in the STOP mode are shown below.
Table 15-2. Operating Status in STOP Mode (1/2)
STOP Mode Setting
Item
When STOP Instruction is Executed While CPU is Operating
When CPU is Operating on
High-speed On-chip Oscillator
Clock (f
IH
)
When CPU is Operating on
X1 Clock (f
X
)
When CPU is Operating on
External Main System Clock
(f
EX
)
System clock
Clock supply to the CPU is
stopped
Main system clock f
IH
Stopped
f
X
f
EX
f
IL
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and bit 4 (WUTMMCK0) of
operation speed mode control register (OSMC)
●
WUTMMCK0 = 1: Oscillates
●
WUTMMCK0 = 0 and WDTON = 0: Stops
●
WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
●
WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM
Illegal-memory access detection
function
Port (latch) Status before STOP mode was set is retained
Timer array unit Operation disabled
12-bit interval timer Operable
Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H)
WDSTBYON = 0: Operation stopped
WDSTBYON = 1: Operation continues
Clock output/buzzer output Operation disabled
A/D converter

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English