Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 9 WATCHDOG TIMER
R01UH0959EJ0110 Rev.1.10 Page 312 of 765
Mar 7, 2023
9.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 9-1. Configuration of Watchdog Timer
Item Configuration
Control register Watchdog timer enable register (WDTE)
How the counter operation is controlled and the overflow time are set by the option byte.
Table 9-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (000C0H)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer (in HALT/STOP mode) Bit 0 (WDSTBYON)
Remark For the option byte, see CHAPTER 18 OPTION BYTE.
Figure 9-1. Block Diagram of Watchdog Timer
Clock Input
controller
Reset
output
controller
Internal bus
Selector
17-bit
counter
Watchdog timer enable register
(WDTE)
Write detector to
WDTE except ACH
Interval time controller
(
2
n
/f
IL
× 0.75)
Overflow signal
f
IL
Internal reset signal
WDCS2
to WDCS0 of option byte
(000C0H)
WDTON of option byte (000C0H)
Interval interrupt request signal
(INTWDTI
)
(2
6
–1 )/f
IL
to (2
16
–1)/f
IL

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English