RL78/G15 CHAPTER 10 A/D CONVERTER
R01UH0959EJ0110 Rev.1.10 Page 335 of 765
Mar 7, 2023
10.6 A/D Converter Operation Modes
The operation of the A/D converter is described below. In addition, the setting procedure is described in 10.7 A/D
Converter Setup Flowchart.
<1> While conversion is stopped, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system
enters the conversion standby state.
<2> After software counts the stabilization wait time (0.125 μs), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion of the analog input specified by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the conversion
standby state.
<5> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the conversion standby state.
<6> When ADCE is cleared to 0 while in the conversion standby state, the A/D converter enters the stop state.
Setting ADCS = 1 and ADCE = 0 is prohibited. Setting ADCS to 1 while conversion is stopped (ADCS = 0, ADCE
= 0) is ignored and A/D conversion does not start.
Figure 10-13. Example of Operation Timing
ADCE
ADCS
ADS
<1> ADCE is set to 1
Conversion is
interrupted
Conver-
sion
standby
Conversion standby Conversion standbyStop state Stop state
<2>ADCS is set to 1 while in
the conversion standby
state
<4>ADCS is automatically cleared
to 0 after conversion ends
<2>
<5>ADCS is cleared to 0
during A
/D conversion
operation
<6> ADCE is set to
0
The trigger is not
acknowledged
The trigger is not
acknowledged
ADS is rewritten (from ANI0 to ANI1)
Data 0
(ANI0)
Data 1
(ANI
1)
Data 1
(ANI1)
Data 0
(ANI0)
Data 0
(ANI0)
A/D conversion
status
ADCR, ADCRH
INTAD
<3> End of A/D conversion
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