Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 11 COMPARATOR
R01UH0959EJ0110 Rev.1.10 Page 360 of 765
Mar 7, 2023
11.5.1 Enabling Comparator Operation (in the Case of CMP0)
Figure 11-8. Procedure for Enabling Comparator Operation
Set the CMPEN bit in PER0 to 1 to supply clock to comparator.
Start
Set the PER0 register
Set the PMC0 and PM0 registers
Set the SPDMD bit
Set the C0VRF bit
Set the C0ENB bit
(Mandatory)
(Mandatory)
(Mandatory)
(Mandatory)
(Mandatory)
Wait for comparator stabilization
(Mandatory)
Set the COMPFIR register
(Optional)
Set the C0OP and C0OE bits
(Optional)
Specify VCOUT0 pin as output
(Optional)
Set interrupt (INTCMP0)
(Optional)
Set the C0IE bit
(Optional)
End
Set the ports for the IVCMP0 and IVREF0 pins to analog input function.
 Set the bits in PMC0 and PM0 to 1.
Set the comparator response speed.
 Set the SPDMD bit in COMPOCR to 1: High-speed mode
 Clear the SPDMD bit in COMPOCR to 0: Low-speed mode
Set the comparator reference voltage.
 Set the C0VRF bit in COMPMDR to 1: Supplied from the internal reference voltage (0.815 V (typ.))
 Clear the C0VRF bit in COMPMDR to 0: Supplied from the IVREF0 pin
Enable comparator operation.
 Set the C0ENB bit in COMPMDR to 1 to enable comparator 0 operation.
Count the comparator output stabilization signals (t
CMP
).
Regarding t
CMP
, see 23. 6. 2 Comparator characteristics and
24. 6. 2 Comparator characteristics.
Enable or disable the digital filter of the comparator and set the effective edge for an interrupt.
 Set the C0FCK1 and C0FCK0 bits in COMPFIR:
00B: Digital filter disabled
01B: Digital filter enabled, sampling clock: f
CLK
10B: Digital filter enabled, sampling clock: f
CLK
/8
11B: Digital filter enabled, sampling clock: f
CLK
/32
 Set the C0EPO and C0EDG bits in COMPFIR:
00B: Rising edge
01B: Falling edge
1xB: Both rising and falling edges
Set the comparator interrupt.
 Specify the interrupt priority level by the CMPPR00 and CMPPR10 bits in PR01H and PR11H.
 Initialize interrupt request by clearing the CMPIF0 bit in IF1H to 0.
 Enable vector interrupt by clearing the CMPMK0 bit in MK1H to 0.
 Enable interrupt request by setting the C0IE bit in COMPOCR to 1.
Output the comparator comparison result from the VCOUT0 pin.
 Set the C0OP bit in COMPOCR:
0B: Non-inverted comparator result is output from the VCOUT0 pin.
1B: Inaverted comparator result is output from the VCOUT0 pin.
 Set the C0OE bit in COMPOCR to 1 to enable output.
 Set the port for the VCOUT0 pin to output function.
Set the bits in PMC0 and PM0 to 1.
Set the bits in P0 to 1.

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English