RL78/G15 CHAPTER 15 STANDBY FUNCTION
R01UH0959EJ0110 Rev.1.10 Page 625 of 765
Mar 7, 2023
15.2 Registers controlling standby function
The standby function is controlled by the following registers.
For details of each register, see CHAPTER 5 CLOCK GENERATOR.
Register which enables or stops the operation of the low-speed on-chip oscillator in the HALT or STOP mode.
●
Operation speed mode control register (OSMC)
Registers which controls oscillation stabilization time of the X1 clock when the STOP mode is released.
●
Oscillation stabilization time counter status register (OSTC)
Note 1
●
Oscillation stabilization time select register (OSTS)
Note 1
Note 1. 16-pin and 20-pin products only.
15.3 Standby Function Operation
15.3.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock
(16-pin and 20-pin products only) or the high-speed on-chip oscillator clock. The operating status in the HALT mode are
shown below.
Caution Because the interrupt request signal is used to clear the HALT mode, if the interrupt mask flag is 0
(the interrupt processing is enabled) and the interrupt request flag is 1 (the interrupt request signal is
generated), the HALT mode is not entered even if the HALT instruction is executed in such a
situation.
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