RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 548 of 765
Mar 7, 2023
13.5.14 Communication reservation
(1) When communication reservation is enabled (bit 0 (IICRSV0) of IICA flag register 0 (IICF0) = 0)
To proceed with master communications next while not currently participating in the bus, a communication reservation
can be made to enable transmission of a start condition when the bus is released. There are two modes for not
participating in the bus.
●
When arbitration results in neither master nor slave operation
●
When an extension code is received and slave operation is disabled (ACK was not returned and the bus was
released by setting bit 6 (LREL0) of IICA control register 00 (IICCTL00) to 1 and exiting from communication)
If bit 1 (STT0) of the IICCTL00 register is set to 1 while not participating in the bus, a start condition is automatically
generated and the wait state is entered after the bus has been released (when a stop condition is detected).
If the address is written to IICA shift register 0 (IICA0) after bit 4 (SPIE0) of the IICCTL00 register is set to 1, and release
of the bus is detected (detection of the stop condition) by generation of an interrupt request signal (INTIICA0), the device
automatically starts communication as the master. Data written to the IICA0 register before detecting the stop condition is
invalid.
When the STT0 bit has been set to 1, the operation mode (operation as start condition or as communication reservation)
is determined according to the state of the bus.
●
If the bus has been released start condition generation
●
If the bus has not been released (standby mode) communication reservation
Check whether the communication reservation operates or not by using the MSTS0 bit (bit 7 of IICA status register 0
(IICS0)) after the STT0 bit is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
Wait time from setting STT0 = 1 to checking the MSTS0 flag:
(
IICWL0 setting value + IICWH0 setting value + 4
)
/f
+ t
× 2
Remark IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F
: SDAA0 and SCLA0 signal falling time
f
CLK
: CPU/peripheral hardware clock frequency
To Next Page
Loading...
Need help?
General
