RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 91 of 765
Mar 7, 2023
3.5.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address
and specifies the target addresses using the result of adding the contents of the B register or C register similarly
specified with the instruction word as the offset address to the base address.
[Operand format]
Identifier Description
—
[HL + B], [HL + C]
(only the space from F0000H to FFFFFH is specifiable)
—
ES:[HL + B], ES:[HL + C]
(higher 4-bit addresses are specified by the ES register)
Figure 3-30. Example of [HL + B], [HL + C]
Instruction code
OP-code
Target memory
FFFFFH
Memory
F
0000
H
•
A pair of registers <1>
specifies the address where the target
array of data starts in the
64-Kbyte area from F0000
H to
FFFFFH
.
•
Either register <
2>
specifies an offset within the array to the
target location in memory
.
<
1> Address of
an array
Target array
of data
rp (
HL)
<2
> Offset
[HL +
B],
<1> <
2>
[HL
+ C
]
<1> <
2>
Other data in the array
r
(B/
C)
Figure 3-31. Example of ES:[HL + B], ES:[HL + C]
Instruction code
OP-code
<3> byte
Target memory
XFFFFH
Memory
X0000H
• The ES register <1> specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of the
address range.
• A pair of registers <2> specifies the address where the target
array of data starts in the 64-Kbyte area specified in the ES
register <1>.
• Either register <3> specifies an offset within the array to the
target location in memory.
ES:
<1>
[HL + B],
<2> <3>
<3>
Offset
Target array
of data
ES
<1>
Specifies a
64-Kbyte area
Other data in the array
<2>
Address of
an array
X0000H
<1>
rp (HL)
ES:
<1>
[HL + C]
<2> <3>
r (B/C)
<2>
<3>
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