RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0959EJ0110 Rev.1.10 Page 613 of 765
Mar 7, 2023
14.3.5 Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an interrupt
request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that control multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. Upon acknowledgment of a
maskable interrupt request, if the value of the priority specification flag register of the acknowledged interrupt is not 00,
its value minus 1 is transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the
PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 14-6. Configuration of Program Status Word
ISP1
Enables interrupts of level 0
(
while an interrupt of level 1 or
0 is being serviced)
Used when normal instruction is executed
6
5 4
3
17
2
0
0
IE Z
RBS1
AC
RBS0
ISP
1
ISP0
CY
PSW
06H
Symbol
After reset
ISP0 Priority of interrupt currently being serviced
0
Enables interrupts of levels 0
and 1
(while an interrupt of level
2 is being serviced)
0
1
Enables interrupts of levels 0
to 2
(while an interrupt of level 3 is being serviced
)
1
0
Enables all interrupts
(wait for acknowledgment of an interrupt)
1
1
IE
0
Interrupt request acknowledgment enable/disable
Disabled
1
Enabled
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