RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 504 of 765
Mar 7, 2023
12.7.6 Procedure for Processing Errors that Occurred during Simplified I
2
C (IIC00,
IIC01) Communication
The procedure for processing errors that occurred during simplified I
2
C (IIC00, IIC01) communication is described in
Figure 12-97 and Figure 12-98.
Figure 12-97. Processing Procedure in Case of Overrun Error
Software Manipulation State of the Hardware Remark
Reads serial data register mn
(SDRmn).
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the next
reception is completed during error
processing.
Reads serial status register mn
(SSRmn).
The error type is identified and the read value
is used to clear the error flag.
Writes 1 to serial flag clear trigger
register mn (SIRmn).
The error flag is cleared.
Only the error during reading can be cleared,
by writing the value read from the SSRmn
register to the SIRmn register without
modification.
Figure 12-98. Processing Procedure in Case of ACK Error in Simplified I
2
C Mode
Software Manipulation State of the Hardware Remark
Reads serial status register mn
(SSRmn).
The error type is identified and the read value
is used to clear the error flag.
Writes serial flag clear trigger register
mn (SIRmn).
The error flag is cleared.
Only the error during reading can be cleared,
by writing the value read from the SSRmn
register to the SIRmn register without
modification.
Sets the STmn bit of serial channel stop
register m (STm) to 1.
The SEmn bit of serial channel enable
status register m (SEm) is set to 0 and
channel n stops operation.
The slave is not ready for reception because
ACK is not returned.
Therefore, a stop condition is created, the bus
is released, and communication is started
again from the start condition. Or, a restart
condition is generated and transmission can
be redone from address transmission.
Creates a stop condition.
Creates a start condition.
Sets the SSmn bit of serial channel
start register m (SSm) to 1.
The SEmn bit of serial channel enable
status register m (SEm) is set to 1 and
channel n is enabled to operate.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), r: IIC number (r = 00, 01), mn = 00, 01
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