RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 545 of 765
Mar 7, 2023
13.5.13 Wakeup function
This is a slave function of I
2
C to generate an interrupt request signal (INTIICA0) when the local address and an extension
code are received.
When the addresses do not match, an unnecessary INTIICA0 signal is not generated to allow efficient processing.
When a start condition is detected, the wakeup standby state is entered. Even a master that has generated a start
condition enters the wakeup standby state while transmitting an address because the master may become a slave due to
an arbitration loss.
To use the wakeup function while in the STOP mode, set the WUP0 bit to 1. The address can be received regardless of
the operation clock. An interrupt request signal (INTIICA0) is also generated when the local address and an extension
code are received. Operation returns to normal operation by using an instruction to clear the WUP0 bit to 0 after this
interrupt has been generated.
Figure 13-21 shows the flow when setting WUP0 = 1 and Figure 13-22 shows the flow when setting WUP0 = 0 upon an
address match.
Figure 13-21. Flow when Setting WUP0 = 1
Yes
No
Wait for 3 clock cycles of f
CLK
MSTS0 = STD0 = EXC0
= COI0 = 0?
WUP0 = 1
Wait
Execute STOP instruction
START
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