RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 408 of 765
Mar 7, 2023
12.5.2 Master Reception
Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from another device.
Simplified SPI CSI00 CSI01
Target channel Channel 0 of SAU0 Channel 1 of SAU0
Pins used SCK00, SO00 SCK01, SO01
Interrupt INTCSI00 INTCSI01
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be
selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate
Note 1
Max. f
CLK
/4 [Hz]
Min. f
CLK
/(2 × 2
15
× 128) [Hz] f
CLK
: System clock frequency
Data phase Selectable by the DAPmn bit of the SCRmn register
●
DAPmn = 0: Data input starts from the start of the operation of the serial clock.
●
DAPmn = 1: Data input starts half a clock cycle before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
●
CKPmn = 0: Non-reverse
●
CKPmn = 1: Reverse
Data direction MSB or LSB first
Note 1. Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics specified in the electrical characteristics. For details, see CHAPTER 23 ELECTRICAL
SPECIFICATIONS (T
A
= −40 to +85°C) and CHAPTER 24 ELECTRICAL SPECIFICATIONS (T
A
= −40 to
+105°C, T
A
= −40 to +125°C).
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01), mn = 00, 01
To Next Page
Loading...
Need help?
General
