RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 55 of 765
Mar 7, 2023
CHAPTER 3 CPU ARCHITECTURE
3.1 Overview
The CPU core of the RL78 microcontroller is based on the Harvard architecture where instruction fetch buses, address
buses, and data buses are kept separate. In addition, through the adoption of three-stage pipeline control of fetch,
decode, and memory access, the operation efficiency is improved drastically over the conventional CPU core. The CPU
core features high performance and highly functional instruction processing, and can be suited for use in various
applications that require high speed and highly functional processing.
The RL78/G15 has the RL78-S2 CPU core. Its main features are as follows.
3-stage pipeline CISC architecture
Address space:
Minimum instruction execution time:
One clock cycle for one instruction
General-purpose register:
-bit registers × 8 × 4 banks
Types of instruction:
Data allocation:
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