RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 552 of 765
Mar 7, 2023
13.5.15 Cautions
(1) When STCEN0 = 0
Immediately after I
2
C operation is enabled (IICE0 = 1), the bus communication state (IICBSY0 = 1) is recognized
regardless of the actual bus state. When performing master communication from the state where a stop condition is not
detected, first generate a stop condition to release the bus, then perform master communication.
When using multiple masters, it is not possible to perform master communication while the bus is not released (a stop
condition is not detected).
Follow the following sequence to generate a stop condition.
<1> Set IICA control register 01 (IICCTL01).
<2> Set bit 7 (IICE0) of IICA control register 00 (IICCTL00) to 1.
<3> Set bit 0 (SPT0) of the IICCTL00 register to 1.
(2) When STCEN0 = 1
Immediately after I
2
C operation is enabled (IICE0 = 1), the bus released state (IICBSY0 = 0) is recognized regardless of
the actual bus state. To generate the first start condition (STT0 = 1), it is necessary to confirm that the bus has been
released, so as to not disturb other communications.
(3) If I
2
C communication with the other party is already in progress
If I
2
C operation is enabled and the device participates in communication already in progress when the SDAA0 pin is at
the low level and the SCLA0 pin is at the high level, the macro of I
2
C recognizes that the SDAA0 pin has changed from
the high to the low level (start condition detection). If the value on the bus at this time can be recognized as an extension
code, ACK is returned, but this interferes with I
2
C communications with the other party. To avoid this, start the I
2
C in the
following sequence.
<1> Clear bit 4 (SPIE0) of the IICCTL00 register to 0 to disable generation of an interrupt request signal (INTIICA0) in
response to the detection of a stop condition.
<2> Set bit 7 (IICE0) of the IICCTL00 register to 1 to enable operation of the I
2
C.
<3> Wait for detection of a start condition.
<4> Set bit 6 (LREL0) of the IICCTL00 register to 1 before ACK is returned (in 4 to 72 clock cycles after setting the
IICE0 bit to 1) to forcibly disable detection.
(4) After setting the STT0 and SPT0 bits (bits 1 and 0 of the IICCTL00 register), re-setting these bits before they are
cleared to 0 is prohibited.
To Next Page
Loading...
Need help?
General
