RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 541 of 765
Mar 7, 2023
(4) Releasing clock stretching
There are four methods for releasing clock stretching as follows.
●
Writing data to the IICA shift register 0 (IICA0)
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Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (releasing clock stretching)
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Setting bit 1 (STT0) of the IICCTL00 register (generating a start condition)
Note 1
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Setting bit 0 (SPT0) of the IICCTL00 register (generating a stop condition)
Note 1
Note 1. Master only
When the clock stretch timing has been set to the falling edge of the 8th clock cycle (WTIM0 = 0), whether or not ACK is
to be generated must be determined before releasing clock stretching.
(5) Stop condition detection
INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1).
13.5.9 Address match detection method
In I
2
C bus mode, the master can select a particular slave device by transmitting the corresponding slave address.
An address match can be detected automatically by the hardware. An INTIICA0 interrupt request is only generated when
the address set in slave address register 0 (SVA0) matches the slave address sent by the master or when an extension
code is received.
13.5.10 Error detection
In I
2
C bus mode, the state of the serial data bus (SDAA0) during transmission is captured in IICA shift register 0 (IICA0)
of the transmitting device, so a transmission error can be detected by comparing the IICA data before the start of
transmission and after the end of transmission. A transmission error is judged to having occurred when the two data
values do not match.
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