RL78/G15 CHAPTER 9 WATCHDOG TIMER
R01UH0959EJ0110 Rev.1.10 Page 314 of 765
Mar 7, 2023
9.4 Operation of Watchdog Timer
9.4.1 Controlling operation of watchdog timer
<1> When the watchdog timer is used, its operation is specified by the option byte (000C0H).
●
Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 18 OPTION BYTE).
WDTON Watchdog Timer Counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
●
Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 9.4.2
Setting time of watchdog timer and CHAPTER 18 OPTION BYTE).
<2> After a reset release, the watchdog timer starts counting.
<3> By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and
before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
<4> If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is also generated in the following cases.
●
If a 1-bit manipulation instruction is executed on the WDTE register
●
If data other than “ACH” is written to the WDTE register
Caution 1. If the watchdog timer is cleared by writing “ACH” to the WDTE register, the actual overflow time
may become shorter than the overflow time set by the option byte by up to one clock cycle of f
IL
.
Caution 2. Clearing the watchdog timer is effective immediately before the counter value overflows.
Caution 3. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on
the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0: Watchdog timer operation stops.
WDSTBYON = 1: Watchdog timer operation continues.
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is released.
At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 clock
Note 1
after releasing the STOP mode, the CPU starts operating
after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode
release and the watchdog timer overflow is short, an overflow occurs during the oscillation
stabilization time, causing a reset. Accordingly, set the overflow time in consideration of the
oscillation stabilization time when operating with the X1 clock after the STOP mode release by an
interval interrupt and the watchdog timer is to be cleared.
Caution 4. Setting WDTON = 0 and WDSTBYON = 1 is prohibited.
Note 1. 16-pin and 20-pin products only
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