RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 87 of 765
Mar 7, 2023
3.5.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as the
base address and specifies the target addresses using the result of adding the 8-bit immediate data or 16-bit immediate
data as the offset data to the base address.
[Operand format]
Identifier Description
—
[HL + byte], [DE + byte], [SP + byte]
(only the space from F0000H to FFFFFH is specifiable)
—
word[B], word[C]
(only the space from F0000H to FFFFFH is specifiable)
—
word[BC]
(only the space from F0000H to FFFFFH is specifiable)
—
ES:[HL + byte], ES:[DE + byte]
(higher 4-bit addresses are specified by the ES register)
—
ES:word[B], ES:word[C]
(higher 4-bit addresses are specified by the ES register)
—
ES:word[BC]
(higher 4-bit addresses are specified by the ES register)
Figure 3-23. Example of [SP + byte]
Instruction code
<1
>
<2> byte
Target memory
FFFFFH
Memory
F0000H
• SP (stack pointer) <
1> indicates the stack as the target
.
• By indicating an offset from the address (top of the stack)
currently pointed to by the stack pointer
, “byte” <2
>
indicates the target memory (
SP + byte).
<1> Specifies a stack
area
Stack area
SP
<2>
Offset
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