RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 539 of 765
Mar 7, 2023
13.5.7 Releasing clock stretching
The I
2
C interface usually releases clock stretching by the following processing.
●
Writing data to IICA shift register 0 (IICA0)
●
Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (releasing clock stretching)
●
Setting bit 1 (STT0) of the IICCTL00 register (generating a start condition)
Note 1
●
Setting bit 0 (SPT0) of the IICCTL00 register (generating a stop condition)
Note 1
Note 1. For the master in I
2
C communications only
When the above processing for releasing clock stretching is executed, I
2
C releases clock stretching and communications
are resumed.
To release clock stretching and transmit data (including the address), write the data to the IICA0 register.
To receive data after clock stretching has been released, or to complete data transmission, set bit 5 (WREL0) of the
IICCTL00 register to 1.
To generate a restart condition after clock stretching has been released, set bit 1 (STT0) of the IICCTL00 register to 1.
To generate a stop condition after clock stretching has been released, set bit 0 (SPT0) of the IICCTL00 register to 1.
Execute the release processing only once for each period of the clock stretch state.
If, for example, data is written to the IICA0 register after clock stretching has been released by setting the WREL0 bit to
1, an incorrect value may be output to the SDAA0 line because the timing for changing the SDAA0 line conflicts with the
timing for writing to the IICA0 register.
In addition to the above, when communications are aborted, clock stretching can be released because clearing the IICE0
bit to 0 stops communications.
If the I
2
C bus has deadlocked due to noise, clock stretching can be released because the device exits from
communications when bit 6 (LREL0) of the IICCTL00 register is set to 1.
Caution If the processing for releasing clock stretching is executed while WUP0 = 1, clock stretching will not
be released.
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