RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 551 of 765
Mar 7, 2023
(2) When communication reservation is disabled (bit 0 (IICRSV0) of IICA flag register 0 (IICF0) = 1)
When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 while the bus is not participating in this
communication during communication, this request is rejected and a start condition is not generated. Non-participation of
the bus in this case includes the following two states.
●
When arbitration results in neither master nor slave operation
●
When an extension code is received and slave operation is disabled (ACK was not returned and the bus was
released by setting bit 6 (LREL0) of the IICCTL00 register to 1 and exiting from communication)
Whether the start condition was generated or rejected can be checked by reading STCF0 (bit 7 of the IICF0 register).
Since up to 5 clock cycles are taken until the STCF0 bit is set to 1 after setting STT0 = 1, secure this time by software.
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