Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 89 of 765
Mar 7, 2023
Figure 3-27. Example of ES:[HL + byte], ES:[DE + byte]
Instruction code
OP-code
<3> byte
Target memory
XFFFFH
Memory
X0000H
• The ES register <1> specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of the
address range.
• Either pair of registers <2> specifies the address where the
target array of data starts in the 64-Kbyte area specified in
the ES register <1>.
• “byte” <3> specifies an offset within the array to the target
location in memory.
ES:
<1>
[HL + byte],
<2> <3>
<3> Offset
Target array
of data
ES
Other data in the array
<2> Address of
an array
X0000H
<1>
rp (HL/DE)
ES:
<1>
[DE + byte]
<2> <3>
<2>
<1>
Specifies a
64-Kbyte area
Figure 3-28. Example of ES:word[B], ES:word[C]
Instruction code
OP-code
Low Addr.
High Addr
.
Target memory
XFFFFH
Memory
X0000H
<2
>
•
The ES register <
1>
specifies a 64-Kbyte area within the
overall 1-
Mbyte space as the four higher-order bits, X
, of
the address range
.
• “word” <
2> specifies the address where the target array of
word
-sized data starts in the 64-
Kbyte area specified in
the ES register <
1>.
• Either register <
3> specifies an offset within the array to
the target location in memory.
ES: word
[B]
,
<
1> <
2> <
3
>
<2>
Address of a word
within an array
Array of
word-
sized
data
ES
<
1> Specifies a
64-Kbyte area
ES:
word [C
],
<1> <2
> <3>
X
0000H
r
(B/C
)
<3>
Offset
<1>
<
3>

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English