R01UH0823EJ0100 Rev.1.00 Page 1052 of 1823
Jul 31, 2019
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.6.4 Receive Data Sampling Timing and Reception Margin
Only the base clock generated by the on-chip baud rate generator can be used as a transmit/receive clock in smart card
interface mode.
In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit
rate according to the settings of the SCMR.BCP2 bit and the SMR.BCP[1:0] bits.
For data reception, the falling edge of the start bit is sampled with the base clock to perform synchronization. Receive
data is sampled on the 16th, 32nd, 186th, 128th, 46th, 64th, 93rd, and 256th rising edges of the base clock so that it can
be latched at the middle of each bit as shown in
Figure 33.37. The reception margin here is determined by the following
formula.
(%)
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula
below.
M = {0.5 – 1/(2 × 372)} × 100 (%) = 49.866 (%)
Figure 33.37 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate)
M0.5
1
2N
--------–


L0.5–F–
D0.5–
N
---------------------
1F+– 100=
Base clock
372 clocks
186 clocks
D0 D1
185 371 0371185 00
Receive data (RXDn)
Synchronization sampling
timing
Data sampling timing
Start bit
186 clocks
372 clocks
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