R01UH0823EJ0100 Rev.1.00 Page 145 of 1823
Jul 31, 2019
RX23W Group 6. Resets
6.3.4 Independent Watchdog Timer Reset
Independent watchdog timer reset is an internal reset generated by the independent watchdog timer.
Output of the independent watchdog timer reset from the independent watchdog timer can be selected by setting the
IWDT reset control register (IWDTRCR) and option function select register 0 (OFS0).
When output of the independent watchdog timer reset is selected, an independent watchdog timer reset is generated if the
independent watchdog timer underflows, or if data is written outside the refresh-permitted period. When the internal
reset time (tRESW2) has elapsed after the independent watchdog timer reset has been generated, the internal reset is
canceled and the CPU starts the reset exception handling.
For details on the independent watchdog timer reset, see
section 31, Independent Watchdog Timer (IWDTa).
6.3.5 Watchdog Timer Reset
The watchdog-timer reset is an internal reset from the watchdog timer.
Output of the independent watchdog timer reset from the independent watchdog timer can be selected by setting the
WDT reset control register (WDTRCR) and option function select register 0 (OFS0).
When output of the independent watchdog timer reset is selected, a watchdog timer reset is generated if the watchdog
timer underflows, or if data is written outside the refresh-permitted period. When the internal reset time (tRESW2) has
elapsed after the watchdog timer reset is generated, the internal reset is canceled and the CPU starts the reset exception
handling.
For details, see
section 30, Watchdog Timer (WDTA).
6.3.6 Software Reset
The software reset is an internal reset generated by the software reset circuit.
When A501h is written to SWRR, a software reset is generated. When the internal reset time (tRESW2) has elapsed after
the software reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.
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