Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 91 of 1823
Jul 31, 2019
RX23W Group 2. CPU
2.8 Number of Cycles
2.8.1 Instruction and Number of Cycle
Table 2.13 to Table 2.20 show the number of cycles in operation of each instruction. The listed numbers of cycles for
access to memory are the numbers of cycles during no-wait access. The operands in the table below indicate the
following meanings.
#IMM: Immediate
flag: bit, flag
Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register
As, Ad: Accumulator
CR: Control register
dsp: displacement
pcdsp: displacement
Note 1. The number of cycles for the dividing instruction varies according to the divisor and dividend.
Note 2. floor (x): Max. integer that is smaller than x.
Table 2.13 Number of Cycles for Arithmetic/logic Instructions
Instruction
Mnemonic
(indicates the common operation when the size is omitted) Number of Cycles
Arithmetic/logic instructions
(register-register, immediate-
register)
 {ABS, NEG, NOT} “Rd”/“Rs, Rd”
 {ADC, MAX, MIN, ROTL, ROTR, XOR} “#IMM, Rd”/“Rs, Rd”
 ADD “#IMM, Rd”/“Rs, Rd”/“#IMM, Rs, Rd”/“Rs, Rs2, Rd”
 {AND, MUL, OR, SUB} “#IMM, Rd”/“Rs, Rd”/“Rs, Rs2, Rd”
 {CMP, TST} “#IMM, Rs”/“Rs, Rs2”
 NOP
 {ROLC, RORC, SAT} “Rd”
 SBB “Rs, Rd”
 {SHAR, SHLL, SHLR} “#IMM, Rd”/“Rs, Rd”/“#IMM, Rs, Rd”
1
 DIV “#IMM, Rd”/“Rs, Rd” 3 to 20*
1
 DIVU “#IMM, Rd”/“Rs, Rd” 2 to 18*
1
 {EMUL, EMULU} “#IMM, Rd”/“Rs, Rd” 2
 SATR 3
Arithmetic/logic instructions
(memory source operand)
 {ADC, ADD, AND, MAX, MIN, MUL, OR, SBB, SUB, XOR}
“[Rs], Rd”/“dsp[Rs], Rd”
 {CMP, TST} “[Rs], Rs2”/“dsp[Rs], Rs2”
3
 DIV “[Rs], Rd / dsp[Rs], Rd” 5 to 22
 DIVU“[Rs], Rd / dsp[Rs], Rd” 4 to 20
 {EMUL, EMULU} “[Rs], Rd”/“dsp[Rs], Rd” 4
 RMPA.B 6+7×floor(n/4)+4×(n%4)
n: Number of processing
bytes*
2
 RMPA.W 6+5×floor(n/2)+4×(n%2)
n: Number of processing
words*
2
 RMPA.L 6+4n
n: Number of processing
longwords*
2

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English