Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1434 of 1823
Jul 31, 2019
RX23W Group 40. SD Host Interface (SDHIa)
40.2.9 SD Interrupt Mask Register 2 (SDIMSK2)
Note 1. When the SDIMSK2.BWEM bit is 0 or the SDIMSK2.BREM bit is 0, set the SDDMAEN.DMAEN bit to 0. When the
SDDMAEN.DMAEN bit is 1, set the SDIMSK2.BWEM bit to 1 and the SDIMSK2.BREM bit to 1.
The SDIMSK2 register enables and disables the interrupt requests from the status flags in the SDSTS2 register. Refer to
Table 40.8 for details on the relationship between the status flags and the requested interrupt source.
SDIMSK2
Address(es): SDHI.SDIMSK2 0008 AC44h
b31 b30 b29 b28 b27 b26 b25 b24
— — — — — — — —
Value after reset:
00000000
b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — —
Value after reset:
00000000
b15 b14 b13 b12 b11 b10 b9 b8
ILAM — — — — —BWEMBREM
Value after reset:
10001011
b7 b6 b5 b4 b3 b2 b1 b0
— RSPTOM ILRM ILWM DTTOM ENDEM CRCEM CMDEM
Value after reset:
01111111
Bit Symbol Bit Name Description R/W
b0 CMDEM
Command Error Interrupt
Request Mask
0: Command error interrupt request not masked
1: Command error interrupt request masked
R/W
b1 CRCEM
CRC Error Interrupt Request
Mask
0: CRC error interrupt request not masked
1: CRC error interrupt request masked
R/W
b2 ENDEM
End Bit Error Interrupt Request
Mask
0: End bit detection error interrupt request not masked
1: End bit detection error interrupt request masked
R/W
b3 DTTOM
Data Timeout Interrupt Request
Mask
0: Data timeout interrupt request not masked
1: Data timeout interrupt request masked
R/W
b4 ILWM
SDBUFR Register Illegal Write
Interrupt Request Mask
0: Illegal write detection interrupt request for the SDBUFR register not
masked
1: Illegal write detection interrupt request for the SDBUFR register
masked
R/W
b5 ILRM
SDBUFR Register Illegal Read
Interrupt Request Mask
0: Illegal read detection interrupt request for the SDBUFR register not
masked
1: Illegal read detection interrupt request for the SDBUFR register
masked
R/W
b6 RSPTOM
Response Timeout Interrupt
Request Mask
0: Response timeout interrupt request not masked
1: Response timeout interrupt request masked
R/W
b7 — Reserved This bit is 0 when read and cannot be modified. R
b8 BREM BRE Interrupt Request Mask
0: Read enable interrupt request for the SDBUFR register not masked
1: Read enable interrupt request for the SDBUFR register masked
R/W
b9 BWEM BWE Interrupt Request Mask
0: Write enable interrupt request for the SDBUFR register not masked
1: Write enable interrupt request for the SDBUFR register masked
R/W
b10 — Reserved This bit is 0 when read and cannot be modified. R
b11 — Reserved This bit is 1 when read and cannot be modified. R
b14 to b12 — Reserved These bits are 0 when read and cannot be modified. R
b15 ILAM
Illegal Access Error Interrupt
Request Mask
0: Illegal access error interrupt request not masked
1: Illegal access error interrupt request masked
R/W
b31 to b16 — Reserved These bits are 0 when read and cannot be modified. R

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English