R01UH0823EJ0100 Rev.1.00 Page 318 of 1823
Jul 31, 2019
RX23W Group 17. Memory-Protection Unit (MPU)
17. Memory-Protection Unit (MPU)
17.1 Overview
The RXv2 CPU incorporates a memory-protection unit that checks the addresses of CPU access to the overall address
space (0000 0000h to FFFF FFFFh).
Access-control information can be set for up to eight regions, and permission for access to each region is in accord with
this information. The default response to the detection of access to a region where permission has not been set is the
generation of a memory-protection error.
The supported access-control information for the individual regions consists of permission to read, permission to write,
and permission to execute. This access-control information is effective when the processor mode of the CPU is user
mode. Memory protection is not applied when the CPU is in supervisor mode.
Table 17.1 lists the specifications of the memory-protection unit, and Figure 17.1 shows a block diagram of the
memory-protection unit.
Table 17.1 Specifications of Memory Protection
Specifictaions Description
Region to be covered by memory protection
and processor mode
0000 0000h to FFFF FFFFh (in user mode)
No memory protection in supervisor mode
Number of regions 8
Page size (smallest unit of protection) 16 bytes
Specifying addresses of individual regions Setting the page numbers where regions start and end
Setting to make memory protection effective
or ineffective in individual regions
A V (valid) bit in each region-n end page number register (REPAGEn) makes the
settings effective or ineffective for the corresponding region (n = 0 to 7).
Access-control information settings for
individual regions
Instruction execution: Permission to execute
Operand access: Permission to read, permission to write
Start of memory-protection operations After the memory-protection unit has been enabled, access monitoring starting up with
the transition to user mode.
Memory-protection error processing Generation of access exceptions
Addresses where memory-protection errors
are generated
Address in instruction execution: The PC value is preserved on the stack.
Address in operand access: The address is stored in the data memory-protection error
address register (MPDEA).
Determining the reasons for memory-
protection errors
The memory-protection error status register (MPESTS) holds indicators of the reason.
Background region setting Access-control information can be set for the background region (the whole address
space).
Processing where regions overlap The access-control information for access to an overlap between regions is the logical
OR of the attributes for the given regions, and permission is given priority.
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