R01UH0823EJ0100 Rev.1.00 Page 717 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.9.4 Conflict between TPUm.TCNT Write and Clear Operations
If the counter clearing signal is generated in a TCNT write cycle, TCNT clearing takes precedence and the TCNT write
is not performed.
Figure 25.44 shows the timing in this case.
Figure 25.44 Conflict between TPUm.TCNT Write and Clear Operations
25.9.5 Conflict between TPUm.TCNT Write and Increment Operations
If incrementing occurs in a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure
25.45
shows the timing in this case.
Figure 25.45 Conflict between TPUm.TCNT Write and Increment Operations
N 0000hTCNT
PCLK
Counter clear signal
TCNT write by CPU
TCNT
PCLK
TCNT input clock
TCNT write by CPU
MX
TCNT write data
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