R01UH0823EJ0100 Rev.1.00 Page 1445 of 1823
Jul 31, 2019
RX23W Group 40. SD Host Interface (SDHIa)
40.2.20 SDHI Software Reset Register (SDRST)
Table 40.5 lists the bits and flags initialized by the SDHI software reset.
SDRST
Address(es): SDHI.SDRST 0008 ADC0h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — — — — — — — — — —
Value after reset:
0000000000000000
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — — — — — — — — —
SDRST
Value after reset:
0000000000000111
Bit Symbol Bit Name Description R/W
b0 SDRST SDHI Software Reset Control
0: SDHI software reset
1: SDHI software reset released
R/W
b2, b1 — Reserved These bits are 1 when read. Set them to 1 when writing. R
b31 to b3 — Reserved These bits are 0 when read and cannot be modified. R
Table 40.5 Bits and Flags Initialized by the SDHI Software Reset
Register Bit/Flag
SDSTOP SDBLKCNTEN
SDSTS1 RSPEND, ACEND
SDSTS2 CMDE, CRCE, ENDE, DTO, ILW, ILR, RSPTO, SDD0MON, BRE, BWE, SDCLKCREN, ILA
SDCLKCR CLKEN
SDOPT CTOP[3:0], TOP[3:0], WIDTH
Bits b8 and b13 in the SDOPT register are also initialized by the SDHI software reset.
SDERSTS1 CMDE0, CMDE1, RSPLENE0, RSPLENE1, RDLENE, CRCLENE, RSPCRCE0, RSPCRCE1, RDCRCE, CRCTKE,
CRCTK[2:0]
SDERSTS2 RSPTO0, RSPTO1, BSYTO0, BSYTO1, RDTO, CRCTO, CRCBSYTO
SDIOSTS IOIRQ, EXPUB52, EXWT
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