R01UH0823EJ0100 Rev.1.00 Page 549 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.3.8 Complementary PWM Mode
In complementary PWM mode, dead time can be set for PWM waveforms to be output. The dead time is the period
during which the upper and lower arm transistors are set to the inactive level in order to prevent short-circuiting of the
arms. Six phases of positive and negative PWM waveforms with dead time can be output by combining MTU3 and
MTU4. PWM waveforms without dead time can also be output.
In complementary PWM mode, MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4B, MTIOC4C, and MTIOC4D pins
function as PWM output pins, and the MTIOC3A pin can be set for toggle output synchronized with the PWM cycle.
Counters MTU3.TCNT and MTU4.TCNT function as up/down-counters.
Table 23.51 lists the PWM output pins used. Table 23.52 lists the settings of the registers used.
A function to directly cut off the PWM output by using an external signal is supported as a port function.
Note 1. Avoid setting the MTIOC3C pin as a timer I/O pin in complementary PWM mode.
Note 1. Access can be enabled or disabled according to the setting in the TRWER register (timer read/write enable register).
Table 23.51 Output Pins for Complementary PWM Mode
Channel Output Pin Description
MTU3 MTIOC3A Toggle output synchronized with PWM cycle (or I/O port)
MTIOC3B PWM output pin 1
MTIOC3C I/O port*
1
MTIOC3D PWM output pin 1' (negative-phase waveform output of PWM output 1)
MTU4 MTIOC4A PWM output pin 2
MTIOC4C PWM output pin 2' (negative-phase waveform output of PWM output 2)
MTIOC4B PWM output pin 3
MTIOC4D PWM output pin 3' (negative-phase waveform output of PWM output 3)
Table 23.52 Register Settings for Complementary PWM Mode
Channel
Counter/
Register Description Read/Write from CPU
MTU3 MTU3.TCNT Starts up-counting from the value set in the dead time register Maskable by TRWER setting*
1
MTU3.TGRA Set MTU3.TCNT upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting*
1
MTU3.TGRB PWM output 1 compare register Maskable by TRWER setting*
1
MTU3.TGRC MTU3.TGRA buffer register Readable/writable
MTU3.TGRD PWM output 1/MTU3.TGRB buffer register Readable/writable
MTU4 MTU4.TCNT Starts up-counting after being initialized to 0000h Maskable by TRWER setting*
1
MTU4.TGRA PWM output 2 compare register Maskable by TRWER setting*
1
MTU4.TGRB PWM output 3 compare register Maskable by TRWER setting*
1
MTU4.TGRC PWM output 2/MTU4.TGRA buffer register Readable/writable
MTU4.TGRD PWM output 3/MTU4.TGRB buffer register Readable/writable
Timer dead time data register
(TDDR)
Set MTU4.TCNT and MTU3.TCNT offset value (dead time value) Maskable by TRWER setting*
1
Timer cycle data register
(TCDR)
Set MTU4.TCNT upper limit value (1/2 carrier cycle) Maskable by TRWER setting*
1
Timer cycle buffer register
(TCBR)
TCDR buffer register Readable/writable
Subcounter (TCNTS) Subcounter for dead time generation Read-only
Temporary register 1 (TEMP1) PWM output 1/MTU3.TGRB temporary register Not readable/writable
Temporary register 2 (TEMP2) PWM output 2/MTU4.TGRA temporary register Not readable/writable
Temporary register 3 (TEMP3) PWM output 3/MTU4.TGRB temporary register Not readable/writable
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