R01UH0823EJ0100 Rev.1.00 Page 750 of 1823
Jul 31, 2019
RX23W Group 26. 8-Bit Timer (TMR)
26.8.4 Conflict between TCNT Write and Increment
Even if a counting-up signal is generated concurrently with CPU write to TCNT, the counting-up is not performed and
the write takes priority as shown in
Figure 26.14.
Figure 26.14 Conflict between TCNT Write and Increment
26.8.5 Conflict between TCORA or TCORB Write and Compare Match
Even if a compare match signal is generated simultaneously with CPU write to TCORA or TCORB as shown in Figure
26.15
, the write takes priority and the compare match signal does not reach High level.
Figure 26.15 Conflict between TCORA or TCORB Write and Compare Match
TCNT count clock
TCNT
PCLK
TCNT write data
TCNT write by CPU
MN
TCNT count clock
TCNT
TCORA or TCORB
PCLK
TCORA or TCORB write data
Not high.
TCORA or TCORB write by CPU
Compare match signal
N + 1N
MN
To Next Page
Loading...
Need help?
General
