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R01UH0823EJ0100 Rev.1.00 Page 1467 of 1823

Jul 31, 2019

RX23W Group 40. SD Host Interface (SDHIa)

40.3.6.10 DMA Transfer

Figure 40.21 shows an example of data being transferred from the SDBUFR register after the CMD18 multi-block read

command is issued.

Figure 40.21 DMA Transfer After CMD18 is Issued

Clear the flag register

Set the SDCLKCR register

Did a response end

or error occur?

Clear the flag and check the response

Issue CMD18 (multi-block read command)

Error (communication error or timeout)

Did an access end

or error occur?

Clear the flag and check the response

Disable DMA transfer from the SDBUFR register

Error (communication error or timeout)

Enable DMA transfer from the SDBUFR register

SDDMAEN register

 0000 0002h

Response end

Access end

SDDMAEN register

 0000 0000h

Start

Set the DMAC or DTC

Error processing (clear the interrupt flags)

(setting to disable DMA transfer from the SDBUFR register)

End

Renesas RX Series User Manual

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