R01UH0823EJ0100 Rev.1.00 Page 1348 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.2.9 RSPI Data Control Register (SPDCR)
Up to four frames can be transmitted or received in one round of transmission or reception activation. The amount of data
in each transfer is controlled by the combination of the SPCMDm.SPB[3:0] bits, the SPSCR.SPSLN[2:0] bits, and the
SPDCR.SPFC[1:0] bits.
When changing the SPDCR.SPFC[1:0] bits while the SPCR.SPE bit is 1, the bits should be changed while the
SPSR.IDLNF flag is 0.
SPFC[1:0] Bits (Number of Frames Specification)
The SPFC[1:0] bits specify the number of frames that can be stored in SPDR (per transfer activation). Up to four frames
can be transmitted or received in one round of transmission or reception, and the amount of data is determined by the
combination of the SPSCR.SPSLN[2:0] bits, and the SPDCR.SPFC[1:0] bits. Furthermore, the setting of the SPFC[1:0]
bits adjusts the number of frames for generation of RSPI receive buffer full interrupt, and start of transmission or
generation of transmit buffer empty interrupts.
When the number of frames of transmit data specified by SPFC[1:0] bits is written to the SPDR register, the
SPSR.SPTEF flag becomes 0 and transmission starts. Then, when the specified number of frames of transmit data has
been transferred to the shift register, the SPTEF flag becomes 1 and the RSPI transmit buffer empty interrupt is
generated.
When the number of frames specified by the SPFC[1:0] bits are received, the SPSR.SPRF flag becomes 1 and the RSPI
receive buffer full interrupt is generated.
Table 38.4 lists the frame configurations that can be stored in SPDR and examples of combinations of settings for
transmission and reception. Do not select the combinations of settings other than those shown in the examples.
Address(es): RSPI0.SPDCR 0008 838Bh
b7 b6 b5 b4 b3 b2 b1 b0
— — SPLW
SPRDT
D
— — SPFC[1:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b1, b0 SPFC[1:0] Number of Frames
Specification
b1 b0
0 0: 1 frame
0 1: 2 frames
1 0: 3 frames
1 1: 4 frames
R/W
b3, b2 — Reserved These bits are read as 0. The write value should be 0. R/W
b4 SPRDTD RSPI Receive/Transmit Data
Select
0: SPDR values are read from the receive buffer
1: SPDR values are read from the transmit buffer
(but only if the transmit buffer is empty)
R/W
b5 SPLW RSPI Longword Access/
Word Access Specification
0: SPDR is accessed in words
1: SPDR is accessed in longwords
R/W
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R/W
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