R01UH0823EJ0100 Rev.1.00 Page 1346 of 1823
Jul 31, 2019
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.2.7 RSPI Sequence Status Register (SPSSR)
SPSSR indicates the sequence control status when the RSPI operates in master mode.
Any writing to SPSSR is ignored.
SPCP[2:0] Bits (RSPI Command Pointer)
The SPCP[2:0] bits indicate SPCMDm that is currently pointed to by the pointer during sequence control by the RSPI.
For the RSPI’s sequence control, refer to
section 38.3.10.1, Master Mode Operation.
SPECM[2:0] Bits (RSPI Error Command)
The SPECM[2:0] bits indicate SPCMDm that is specified by the SPCP[2:0] bits when an error is detected during
sequence control by the RSPI. The RSPI updates the SPECM[2:0] bits only when an error is detected. If both the
SPSR.OVRF and SPSR.MODF flags are 0 and there is no error, the values of the SPECM[2:0] bits have no meaning.
For the RSPI’s error detection function, refer to
section 38.3.8, Error Detection. For the RSPI’s sequence control, refer
to
section 38.3.10.1, Master Mode Operation.
Address(es): RSPI0.SPSSR 0008 8389h
b7 b6 b5 b4 b3 b2 b1 b0
— SPECM[2:0] — SPCP[2:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b2 to b0 SPCP[2:0] RSPI Command Pointer
b2 b0
000: SPCMD0
001: SPCMD1
010: SPCMD2
011: SPCMD3
100: SPCMD4
101: SPCMD5
110: SPCMD6
111: SPCMD7
R
b3 — Reserved This bit is read as 0. R
b6 to b4 SPECM[2:0] RSPI Error Command
b6 b4
000: SPCMD0
001: SPCMD1
010: SPCMD2
011: SPCMD3
100: SPCMD4
101: SPCMD5
110: SPCMD6
111: SPCMD7
R
b7 — Reserved This bit is read as 0. R