R01UH0823EJ0100 Rev.1.00 Page 597 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
23.6.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in a TCNT write cycle, the TCNT counter clearing takes precedence and the
TCNT counter write operation is not performed.
Figure 23.97 shows the timing in this case.
Figure 23.97 Contention between TCNT Write and Counter Clear Operations
23.6.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in a TCNT write cycle, the TCNT counter write operation takes precedence and the TCNT
counter is not incremented.
Figure 23.98 shows the timing in this case.
Figure 23.98 Contention between TCNT Write and Increment Operations
TCNT
PCLK
Written by CPU
N 0000h
Counter clear signal
N
TCNT write data
TCNT
PCLK
TCNT count clock
Written by CPU
N M
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