R01UH0823EJ0100 Rev.1.00 Page 719 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.9.8 Conflict between TPUm.TGRy Read and Input Capture
If the input capture signal is generated in a TGRy read cycle, the data that is read will be the data before input capture
transfer.
Figure 25.48 shows the timing in this case.
Figure 25.48 Conflict between TPUm.TGRy Read and Input Capture
25.9.9 Conflict between TPUm.TGRy Write and Input Capture
If the input capture signal is generated in a TGRy write cycle, the input capture operation takes precedence and the write
to TGRy is not performed.
Figure 25.49 shows the timing in this case.
Figure 25.49 Conflict between TPUm.TGRy Write and Input Capture
Internal data bus
TGRy
PCLK
Input capture signal
Buffer register read by CPU
M
N
N
TCNT write by CPU
TCNT
TGRy
PCLK
Input capture signal
M
M
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