Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 753 of 1823
Jul 31, 2019
RX23W Group 26. 8-Bit Timer (TMR)
26.8.8 Clock Source Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, count clocks for TMR0.TCNT and
TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) are not generated, and the counter stops. Do not specify 16-bit counter
mode and compare match count mode simultaneously.
26.8.9 Continuous Output of Compare Match Interrupt Signal
When TCORA or TCORB is set to 00h, PCLK/1 is set as the internal clock, and compare match is set as the counter clear
source, the TCNT counter remains 00h and is not updated, and a compare match interrupt signal is output continuously to
form a flat signal level.
At this time, the interrupt controller cannot detect the second and subsequent interrupts.
Figure 26.16 shows operation timing when the compare match interrupt signal is continuously output.
Figure 26.16 Continuous Output of Compare Match Interrupt Signal (n = 0 to 3)
Counter clear signal
TCORA or TCORB
PCLK
TCNT
00h
CMIAn or CMIBn
00h
00h
08h
TCCR
Compare match signal
Start supplying the internal clock PCLK/1

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English