R01UH0823EJ0100 Rev.1.00 Page 680 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.2.9 Timer Synchronous Register (TSYR)
Note 1. To set synchronous operation, the SYNCn bit (n = 0 to 5) for at least two channels must be set to 1. To set synchronous
clearing, the TCNT clearing source must also be set by the TCR.CCLR[2:0] bits in addition to the SYNCn bit.
TPU.TSYR selects independent operation or synchronous operation for TCNT of TPU0 to TPU5.
SYNCn Bit (Timer Synchronization n) (n = 0 to 5)
This bit selects whether the TCNT operation is independent of or synchronized with TCNT of other channels.
When synchronous operation is selected, synchronous setting of multiple TCNT and synchronous clearing through
counter clearing on another channel are possible.
Address(es): TPU.TSYR 0008 8101h
b7 b6 b5 b4 b3 b2 b1 b0
— — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 SYNC0 Timer Synchronization 0 0: TCNT operates independently
(TCNT setting/clearing is unrelated to other channels)
1: TCNT performs synchronous operation*
1
(TCNT synchronous setting/synchronous clearing is possible)
R/W
b1 SYNC1 Timer Synchronization 1 R/W
b2 SYNC2 Timer Synchronization 2 R/W
b3 SYNC3 Timer Synchronization 3 R/W
b4 SYNC4 Timer Synchronization 4 R/W
b5 SYNC5 Timer Synchronization 5 R/W
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R/W
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