R01UH0823EJ0100 Rev.1.00 Page 654 of 1823
Jul 31, 2019
RX23W Group 24. Port Output Enable 2 (POE2a)
(2) Low-Level Detection
Figure 24.3 shows the low-level detection operation. When a low level is detected 16 times continuously with the
sampling clock selected by the ICSR1 and ICSR2 registers, the detected level is recognized as low, and the pins for the
MTU complementary PWM output and MTU0 are placed in high-impedance. If even one high level is detected during
this interval, the detected level is not recognized as low. Furthermore, in an interval over which the sampling clock is not
being output, changes to the levels on the POE0#, POE1#, POE3# and POE8# pins are ignored.
Figure 24.3 Low-Level Detection Operation
24.3.2 Output-Level Compare Operation
Figure 24.4 shows an example of the output-level compare operation for the combination of MTIOC3B and MTIOC3D
(MTU complementary PWM output pins). The operation is the same for the other pin combinations.
Figure 24.4 Output-Level Compare Operation
PCLK
Sampling clock
POE# input
MTIOC3B
When high level is
sampled at least once
When low level is
sampled at all points
[1]
High-impedance*
1
Flag set (POE# received)
Flag not set
[1]
[2]
[2]
[3]
[16]
[13][0]
8/16/128 clock cycles
Note 1. The other MTU complementary PWM output pins and MTU0 pins also enter the high-impedance in the similar timing.
MTIOC3B
MTIOC3D
High-impedance
Active level overlapping detected*
1
PCLK
Note 1. In this case, the low level has been set as the active level for the MTIOC3B and MTIOC3D pins.
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