R01UH0823EJ0100 Rev.1.00 Page 784 of 1823
Jul 31, 2019
RX23W Group 28. Realtime Clock (RTCe)
28.2.20 Time Error Adjustment Register (RADJ)
Adjustment is performed by the addition to or subtraction from the prescaler.
In case when the automatic adjustment enable (RCR2.AADJE) bit is 0, adjustment is performed when writing to the
RADJ.
In case when the RCR2.AADJE bit is 1, adjustment is performed in the interval specified by the automatic adjustment
period select (RCR2.AADJP) bit.
The current adjustment by software (disabling automatic adjustment) may be invalid if the following adjustment value is
specified within 320 cycles of the count source after the register setting. To perform adjustment consecutively, wait for
320 cycles or more of the count source after the register setting and then specify the next adjustment value.
RADJ is updated in synchronization with the count source. When RADJ is modified, check that all the bits have been
updated before continuing with further processing.
This register is set to 00h by an RTC software reset.
ADJ[5:0] Bits (Adjustment Value)
These bits specify the adjustment value (the number of sub-clock cycles) from the prescaler.
PMADJ[1:0] Bits (Plus–Minus)
These bits select whether the clock is set ahead or back depending on the error-adjustment value set in the ADJ[5:0] bits.
Address(es): RTC.RADJ 0008 C42Eh
b7 b6 b5 b4 b3 b2 b1 b0
PMADJ[1:0] ADJ[5:0]
Value after reset:
xxxxxxxx
x: Undefined
Bit Symbol Bit Name Description R/W
b5 to b0 ADJ[5:0] Adjustment Value These bits specify the adjustment value from the prescaler. R/W
b7, b6 PMADJ[1:0] Plus–Minus
b7 b6
0 0: Adjustment is not performed.
0 1: Adjustment is performed by the addition to the prescaler.
1 0: Adjustment is performed by the subtraction from the prescaler.
1 1: Setting prohibited
R/W
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