R01UH0823EJ0100 Rev.1.00 Page 1315 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
37.2.7 TDM Mode Register (SSITDMR)
Note 1. This bit can be set only in master mode (SSICR.SCKD bit = 1 and SSICR.SWSD bit = 1).
The SSITDMR register is a readable/writable 32-bit register that enables or disables WS continue mode.
Address(es): SSI0.SSITDMR 0008 A520h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
————————————————
Value after reset:
0000000000000000
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
———————CONT————————
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b7 to b0 — Reserved These bits are read as 0. The write value should be 0. R/W
b8 CONT WS Continue Mode*
1
0: Disables WS continue mode.
1: Enables WS continue mode.
R/W
b31 to b9 — Reserved These bits are read as 0. The write value should be 0. R/W
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