R01UH0823EJ0100 Rev.1.00 Page 679 of 1823
Jul 31, 2019
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa)
25.2.8 Timer Start Register (TSTR)
TPU.TSTR starts or stops TCNT operation for TPU0 to TPU5.
Before setting the operating mode in TPUm.TMDR or setting the TPUm.TCNT count clock in TPUm.TCR, stop the
TPUm.TCNT operation.
CSTn Bit (Counter Start n) (n = 0 to 5)
This bit starts or stop the TCNT.
When the CSTn bit is cleared to 0 with CSTn = 1 and the corresponding TIOCyn pin (y = A to D; n = 0 to 5) specified for
output, count operation stops but the output compare output level of the corresponding TIOCyn pin is retained.
If TIORH, TIORL, or TIOR is written to when the CSTn bit is 0, the pin output level will be changed to the set initial
output value.
Address(es): TPU.TSTR 0008 8100h
b7 b6 b5 b4 b3 b2 b1 b0
— — CST5 CST4 CST3 CST2 CST1 CST0
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 CST0 Counter Start 0 0: TCNT count operation is stopped
1: TCNT performs count operation
R/W
b1 CST1 Counter Start 1 R/W
b2 CST2 Counter Start 2 R/W
b3 CST3 Counter Start 3 R/W
b4 CST4 Counter Start 4 R/W
b5 CST5 Counter Start 5 R/W
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R/W
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