R01UH0823EJ0100 Rev.1.00 Page 1329 of 1823
Jul 31, 2019
RX23W Group 37. Serial Sound Interface (SSI)
37.3.7 Serial Bit Clock Control
The SSI controls and selects the serial bit clock, according to the SSICR.SCKD and CKDV[3:0] bits setting.
If the serial bit clock direction is set to input (SCKD bit = 0), this module is in slave mode and the shift register uses the
clock that was input to the SSISCK0 pin as the bit clock.
If the serial bit clock direction is set to output (SCKD bit = 1), this module is in master mode, and the shift register uses
the master clock (MCLK) or a divided master clock as the bit clock. The master clock is divided by the ratio specified by
the SSICR.CKDV[3:0] bits for use as the bit clock by the shift register.
In either case the module pin, SSISCK0, is the same as the bit clock.
37.4 Interrupt Sources
Table 37.7 lists the interrupt sources of the SSI. Each interrupt source can be enabled or disabled by the SSICR.TUIEN,
TOIEN, RUIEN, ROIEN and IIEN bits, and the SSIFCR.TIE and RIE bits.
Table 37.7 SSI Interrupt Sources
Channel
Interrupt
Source Description
Interrupt Status
Flag
Interrupt Enable
Bit
DMAC/DTC
Start Trigger
SSI0 SSIF0 Transmit underflow interrupt
Transmit overflow interrupt
Receive underflow interrupt
Receive overflow interrupt
Idle interrupt
SSISR.TUIRQ
SSISR.TOIRQ
SSISR.RUIRQ
SSISR.ROIRQ
SSISR.IIRQ
SSICR.TUIEN
SSICR.TOIEN
SSICR.RUIEN
SSICR.ROIEN
SSICR.IIEN
Not available
SSIRXI0 Receive data full interrupt (RXI) SSIFSR.RDF SSIFCR.RIE Available
SSITXI0 Transmit data empty interrupt (TXI) SSIFSR.TDE SSIFCR.TIE Available
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