Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 518 of 1823
Jul 31, 2019
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
NFCS[1:0] Bits (Noise Filter Clock Select)
These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the
selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, selecting
the external clock as the source to drive counting, wait for two cycles of the external clock before setting the input-
capture function.
23.2.31 Bus Master Interface
The timer counters (TCNT), timer general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register
(TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request
control register (TADCR), timer A/D converter start request cycle set registers (TADCORA/TADCORB), and timer A/D
converter start request cycle set buffer registers (TADCOBRA/TADCOBRB) are 16-bit registers. A 16-bit data bus to the
bus master enables 16-bit read/write access. 8-bit read/write is not allowed. Access the registers in 16-bit units.
All registers other than the above registers are 8-bit registers, so read/write access should be performed in 8-bit units.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English