Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 1648 of 1823
Jul 31, 2019
RX23W Group 47. Comparator B (CMPBa)
47.3.1 Comparator Bn Digital Filter (n = 2, 3)
The sampling clock can be selected by the CPB1F.CPBnF[1:0] bits. The CPBnOUT signal (internal signal) output from
comparator Bn is sampled at every sampling clock cycle. At the next clock timing after the level matches three times, the
IR104.IR flag (when comparator B2 selected) or IR105.IR flag (when comparator B3 selected) is set to 1 (interrupt
requested).
Figure 47.5 shows the configuration of the comparator Bn digital filter, and Figure 47.6 shows an operating example of
the comparator Bn digital filter.
Figure 47.5 Configuration of Comparator Bn Digital Filter (n = 2, 3)
Figure 47.6 Operating Example of Comparator Bn Digital Filter (n = 2, 3)
00b
01b
11b
PCLK
PCLK/8
PCLK/64
Sampling clock
1
CPBnFEN
0
To comparator
Bn interrupt
CPBnINTEN
CPBnINTPL
0 : Falling-edge detection
1 : Rising-edge detection
10b
PCLK/32
CPBnF[1:0]
CPBnINTEG
CMPBn
CVREFBn
Digital filter
(3 times
match)
Single-edge
and polarity
detection
circuit
Both-edge
detection
circuit
0
1
CPBnOUT
CPBnF[1:0] and CPBnFEN: Bits in the CPB1F register
CPBnINTEN and CPBnINTPL: Bits in the CPB1INT register
CPBnOUT signal
(internal signal)
Sampling timing
Set to 0 by program,
or becomes 0 when the interrupt request is
accepted by the interrupt request destination
This is an operating example in which the CPB1F.CPBnFEN bit is set to 1 (digital filter used).
IR104.IR flag (comparator B2)
IR105.IR flag (comparator B3)

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English