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R01UH0823EJ0100 Rev.1.00 Page 943 of 1823

Jul 31, 2019

RX23W Group 32. USB 2.0 Host/Function Module (USBc)

32.3.6 Control Transfers Using DCP

In the data stage of control transfers, data is transferred using the default control pipe (DCP).

The DCP buffer memory is a 64-byte single buffer and is a fixed area that is shared for both control reading and control

writing. The buffer memory can be accessed only through the CFIFO port.

32.3.6.1 Control Transfers When the Host Controller is Selected

(1) Setup Stage

Registers USBREQ, USBVAL, USBINDX, and USBLENG are the registers that are used to transmit a USB request for

setup transactions. Writing setup packet data to the registers and writing 1 to the DCPCTR.SUREQ bit transmits the

specified data for setup transactions. Upon completion of the transaction, the SUREQ bit is set to 0. The above USB

request registers should not be modified while SUREQ = 1.

After the attached state of the connected function device is detected, the first setup transaction for the device should be

issued by using the sequence described above with the DCPMAXP.DEVSEL[3:0] bits set to 0 and the

DEVADD0.USBSPD[1:0] bits set appropriately.

After the connected function device is shifted to the Address state, setup transactions should be issued by using the

sequence described above with the assigned USB address set in the DEVSEL[3:0] bits and the bits in the DEVADDn

0010b, make appropriate settings in the DEVADD2 register; when PIPEMAXP.DEVSEL[3:0] = 0101b, make

appropriate settings in the DEVADD5 register.

When the setup transaction data has been sent, an interrupt request is generated according to the response received from

the peripheral device (SIGN or SACK flag in the INTSTS1 register), by means of which the result of the setup

transactions can be confirmed.

A data packet of DATA0 (USB request) is transmitted as the data packet for a setup transaction regardless of the setting

of the DCPCTR.SQMON flag.

(2) Data Stage

Data is transferred using the DCP buffer memory.

The access direction of the DCP buffer memory should be specified using the CFIFOSEL.ISEL bit. The transfer

direction should be specified using the DCPCFG.DIR bit.

For the first data packet of the data stage, the data PID should be transferred as DATA1. Set data PID = DATA1 in the

DCPCTR.SQSET bit and the PID[1:0] bits = 01b (BUF). Completion of data transfer is detected using the BRDY or

BEMP interrupt.

For control write transfers, when the number of data bytes to be sent is an integer multiple of the maximum packet size,

software should control so as to send a zero-length packet at the end.

(3) Status Stage

Zero-length packet data is transferred in the direction opposite to that in the data stage. As in the data stage, data is

transferred using the DCP buffer memory. Transactions are done in the same manner as the data stage.

For the data packets of the status stage, the data PID should be set to DATA1 using the DCPCTR.SQSET bit.

For reception of a zero-length packet, the received data length should be confirmed using the CFIFOCTR.DTLN[8:0]

flags after a BRDY interrupt is generated, and the buffer memory should then be cleared using the CFIFOCTR.BCLR

bit.

Renesas RX Series User Manual

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