Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 92 of 1823
Jul 31, 2019
RX23W Group 2. CPU
Note 1. When the load data is used by the subsequent instruction, the number of cycles described as “latency” is counted as the number
of cycles for the memory load instruction. For the cycles other than the memory load instruction, the number of cycles described
as “throughput” is counted.
Note 2. The POPM instruction is converted into multiple load operations. The processing is the same as the one for the load operations
of the MOV instruction, where the operation is repeated for the number of specified registers.
Note 3. The PUSHM instruction is converted into multiple store operations. The processing is the same as the one for the store
operations of the MOV instruction, where the operation is repeated for the number of specified registers.
Table 2.14 Number of Cycles for Transfer Instructions
Instruction
Mnemonic
(indicates the common operation when the size is omitted) Number of Cycles
Transfer instructions
(register-register, immediate-
register)
 MOV “#IMM, Rd”/“Rs, Rd”
 {MOVU, REVL, REVW} “Rs, Rd”
 SCCnd “Rd”
 {STNZ, STZ} “#IMM, Rd”/ “Rs, Rd”
1
 XCHG “Rs, Rd” 2
Transfer instructions
(load operation)
 {MOV, MOVU} “[Rs], Rd”/“dsp[Rs], Rd”/“[Rs+], Rd”/“[-Rs],
Rd”/“[Ri, Rb], Rd”
 MOVLI “[Rs], Rd”
 POP “Rd”
Throughput: 1
Latency: 2*
1
 POPC “CR” Throughput: 3
Latency: 4*
1
 POPM “Rd-Rd2” Throughput: n
Latency: n+1
n: Number of registers*
1,
*
2
Transfer instructions
(store operation)
 MOV “Rs, [Rd]”/“Rs, dsp[Rd]”/“Rs, [Rd+]”/“Rs, [-Rd]”/“Rs, [Ri,
Rb]”/“#IMM, dsp[Rd]”/“#IMM, [Rd]”
 PUSH “Rs”
 PUSHC “CR”
 SCCnd “[Rd]”/“dsp[Rd]”
 MOVCO “Rs, [Rd]”
1
 PUSHM “Rs-Rs2” n
n: Number of registers*
3
Transfer instructions
(memory-register)
 XCHG “[Rs], Rd”/“dsp[Rs], Rd” 2
Transfer instructions
(memory-memory)
 MOV “[Rs], [Rd]”/“dsp[Rs], [Rd]”/“[Rs], dsp[Rd]”/“dsp[Rs],
dsp[Rd]”
 PUSH “[Rs]”/“dsp[Rs]”
3
Table 2.15 Number of Cycles for Bit Manipulation Instructions
Instruction
Mnemonic
(indicates the common operation when the size is omitted) Number of Cycles
Bit manipulation instructions
(register)
 {BCLR, BNOT, BSET} “#IMM, Rd”/“Rs, Rd”
 BMCnd “#IMM, Rd”
 BTST “#IMM, Rs”/“Rs, Rs2”
1
Bit manipulation instructions
(memory source operand)
 {BCLR, BNOT, BSET} “#IMM, [Rd]”/“#IMM, dsp[Rd]”/“Rs,
[Rd]”/“Rs, dsp[Rd]”
 BMCnd “#IMM, [Rd]”/“#IMM, dsp[Rd]”
 BTST “#IMM, [Rs]”/“#IMM, dsp[Rs]”/“Rs, [Rs2]”/“Rs,
dsp[Rs2]”
3

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English