R01UH0823EJ0100 Rev.1.00 Page 238 of 1823
Jul 31, 2019
RX23W Group 11. Low Power Consumption
RSTCKEN Bit (Sleep Mode Return Clock Source Switching Enable)
The RSTCKEN bit enables or disables clock source switching when sleep mode is exited.
The clock source can be switched when exiting sleep mode only while the sub-clock oscillator is selected as the clock for
entering sleep mode. Do not enable this bit when entering sleep mode while the HOCO, LOCO, main clock oscillator, or
PLL is selected as the clock source.
When returning from sleep mode while this bit is enabled, the SOPCM bit in the SOPCCR register is automatically
rewritten to 0 (middle-speed operating mode or high-speed operating mode).
The value of the frequency division setting (in the SCKCR register) is retained.
To exit sleep mode to middle-speed operating mode when the main clock oscillator is selected, the frequency of each
clock must be lower than 12 MHz when the power supply voltage is 2.4 V or above, and lower than 8 MHz when the
voltage is below 2.4 V.