Renesas RX Series User Manual

R01UH0823EJ0100 Rev.1.00 Page 392 of 1823
Jul 31, 2019
RX23W Group 19. Data Transfer Controller (DTCa)
Figure 19.4 Operation Flowchart of the DTC
Start
Compare vector
numbers. Match?
Read DTC vector
Unmatch or RRS bit = 0
Read transfer information
Transfer data
Write back
transfer information
End
Transfer data
Write back
transfer information
ICU.DTCERn.DTCE
bit is cleared
An interrupt to the
CPU is generated
Last data transfer?
(Transfer counter = 1?)
*1
No
Yes
DISEL bit = 1?
No
Yes
Clear interrupt status flag
Update start address
of transfer information
CHNE bit = 1?
No
Yes
CHNS bit = 0?
No
Yes
Last data transfer?
(Transfer counter = 1?)
*1
No
Yes
An interrupt to the
CPU is generated
Transfer data
Write back
transfer information
Transfer data
Write back
transfer information
Next transfer
MD[1:0] bits = 01b?
(Repeat transfer mode?)
No
Yes
Match and
RRS bit = 1
Note 1. Counter value before starting data transfer.

Renesas RX Series Specifications

General

Brand	Renesas
Model	RX Series
Category	Microcontrollers
Language	English